Interrupts and Exceptions

<b style="font-size: large; font-family: Verdana; line-height: 1.5;">Introduction</b><br/><br/>Much of the functionality embedded inside a personal computer is implemented by hardware devices other than the processor. For example, serial communication is handled by an Intel 8251A chip (or a 16550AF in newer computers), which is located on the computer's motherboard (usually inside an ASIC) while the keyboard is controlled by a 8042A microprocessor.<br/><br/>Since each device operates at its own pace, a method is needed for synchronizing the operation of the processor with these devices. One solution is for the processor to sit in a tight loop, asking each device about its current state (a method known as polling). When data is available in one of the devices, the processor can then read and process the incoming bytes. While this method works, it has many disadvantages. First, it is very wasteful in terms of processing power, since the processor is constantly busy reading the status of the attached devices instead of executing some useful code. And second, when the rate of data transfer is extremely high, the processor might lose data bytes arriving from the hardware devices.<br/><br/>So, a different approach was devised. Instead of polling hardware devices to wait for their response, each device is responsible for notifying the processor about its current state. When a hardware device needs the processor's attention, it simply sends an electrical signal (hardware interrupt) through a dedicated pin in the interrupt controller chip (located on the computer's motherboard).<br/><br/>The interrupt controller serves as an intermediate between the hardware devices and the processor. Its responsibility is to alert the processor when one of the hardware devices needs its immediate attention. In this case, the processor stops its current activity and jumps to execute a function (interrupt handler) which was previously associated with the calling device (or more accurately, associated with the interrupt vector of the device).<br/><br/>While hardware interrupts have a significant importance, software interrupts also play a major role in the normal operation of the PC. These interrupts are synchronous rather than asynchronous, since they are generated by the processor itself when it encounters an INT instruction inside the code stream. Software interrupts are usually used by the operating system to publish its internal functions, thereby allowing applications to take advantage of these services.<br/><br/>Exceptions belong to a special type of software interrupts. They are generated by the processor itself whenever some unexpected critical event occurs. For instance, a page fault exception (interrupt 14) is triggered when the processor attempts to access a page, which is marked as not-present. The exception handler can then reload the page from disk (virtual memory) and restart the instruction which generated the exception.<br/><br/>Three types of exceptions can be generated by the processor: faults, traps and aborts. When a fault exception occurs, the CS and (E)IP registers which are pushed on the stack, point to the address of the instruction, which generated the exception. This gives the exception handler a chance to fix the condition which caused the exception to occur, before restarting the faulting instruction. Traps are similar to interrupts in the sense that they make the processor push the address of the next instruction to the stack, while aborts neglect to specify the location of the faulting instruction, since they are usually used to indicate severe errors (such as hardware errors or illegal system tables) which are not recoverable.<br/><br/><hr /><br/><br/> <br/><br/><span style="font-family: Verdana; font-size: small;"><span style="font-size: large;"><b>Real-Mode</b></span></span><br/><br/><span style="font-size: medium;"><b>Software Interrupts</b></span><br/><br/>If you've ever programmed for DOS, you probably know that the INT 21h interface has a salient importance in linking applications with operating system services. For instance, calling an operating system function for opening a file, simply requires issuing an INT 21h interrupt with the correct parameters set in the processor registers.<br/><br/>The BIOS (Basic Input Output System) uses a similar software communication mechanism. The INT 10h, 13h and 16h are all interfaces to internal BIOS functions, which control the screen, the disk controller and the keyboard. Instead of accessing hardware devices directly, DOS uses the BIOS services to control the operation of the system. Modern operating systems such as Windows NT drop their reliance upon the BIOS in favor of faster mechanisms (device drivers) for accessing the PC's hardware.<br/><br/>When the processor bumps into an INT instruction, it pushes the address of the next instruction (CS and IP registers) and the contents of its flags register to the stack and then jumps to execute the interrupt handler. This ensures that when the handler code ends, the processor returns automatically to the original code stream (the code which was executing before the interrupt occured).<br/><br/>Here are the precise steps taken by the processor when it encounters an INT instruction:<br/><ol><br/> <li>Push Flags, CS and IP to the stack (in this order).</li><br/> <li>Multiply interrupt number by 4 and use the resulting number as an offset into the interrupt table (located at the beginning of the physical address space).</li><br/> <li>Get far address (CS and IP) of the interrupt handler from the table entry.</li><br/> <li>Disable interrupts (note that if you wish hardware interrupts to be serviced even when the processor executes inside an interrupt handler, you must issue a STI instruction at the beginning of the handler code).</li><br/> <li>Jump to execute the handler.</li><br/> <li>When the handler code ends (an IRET instruction is executed), pop CS, IP and the flags from the stack so that control returns to the currently active application.</li><br/></ol><br/>Many applications (especially TSRs - Terminate and Stay Resident programs) hook software interrupts to supply additional services on top of those offered by DOS and the BIOS. One good example is Netware 3.1, which hooks INT 21h in order to add support for network file operations (such as reading a file located on a remote computer). Other pieces of code (mostly device drivers) hook hardware interrupts to monitor various devices and ensure their proper operation.<br/><br/>To hook an interrupt, a program need only to replace a specific interrupt table entry with the address of its own interrupt handler. Whenever this interrupt occurs, the handler is automatically invoked by the processor. A good programming practice is to place a call to the previous handler inside the interrupt handling function. This ensures that all previously installed hooks will get a chance to handle the incoming interrupt.<br/><br/>Note that when loading an application which uses software interrupts to call operating system services, there is no need to patch the application code with the actual memory addresses of the OS services. Therefore, the operating system can freely relocate its services in memory by simply updating the corresponding interrupt table entries with the new addresses.<br/><br/><span style="font-family: Verdana; font-size: small;"><span style="font-size: medium;"><b>Hardware Interrupts</b></span></span><br/><br/>Hardware interrupts are not very different in behavior. But still, when considering the path traveled by a hardware interrupt from the instant it leaves the hardware device until it reaches the processor, you must take into account the actions taken by the interrupt controller (or the 8259A if you prefer).<br/><br/>When the processor executes an INT instruction, it retrieves the interrupt code from the opcode itself. This code is later used by the processor to index the <b>IVT</b> (interrupt vector table) and find the address of the interrupt handler. On the other hand, when a hardware interrupt is detected, the interrupt controller sends the interrupt code to the processor via the data bus. When the code is finally acquired by the processor (either from the INT opcode or from the interrupt controller) the steps taken are equivalent to those discussed earlier.<br/><br/>Table 1 presents the interrupt vectors occupied by the interrupt controller chips under different operating systems:<br/><table border="0" width="50%" cellspacing="1" cellpadding="4" bgcolor="#A3D9F5"><br/><tbody><br/><tr><br/><th bgcolor="#8FB6DF"><span style="font-family: Verdana; font-size: small;"><i>OS</i></span></th><br/><th bgcolor="#8FB6DF"><span style="font-family: Verdana; font-size: small;"><i>Vectors occupied by the master 8259A</i></span></th><br/><th bgcolor="#8FB6DF"><span style="font-family: Verdana; font-size: small;"><i>Vectors occupied by the slave 8259A</i></span></th><br/></tr><br/><tr><br/><td><center>DOS</center></td><br/><td><center>8h - Fh</center></td><br/><td><center>70h - 77h</center></td><br/></tr><br/><tr><br/><td><center>Windows 95 / 98</center></td><br/><td><center>50h - 57h</center></td><br/><td><center>58h - 5Fh</center></td><br/></tr><br/><tr><br/><td><center>Windows NT</center></td><br/><td><center>30h - 37h</center></td><br/><td><center>38h - 3Fh</center></td><br/></tr><br/></tbody><br/></table><br/><span style="font-family: Verdana; font-size: small;"><span style="font-size: xx-small;">Table 1 - Interrupt vectors occupied by the 8259A chips</span></span><br/><br/><hr /><br/><br/> <br/><br/><span style="font-family: Verdana; font-size: small;"><span style="font-size: medium;"><b>Exceptions</b></span></span><br/><br/>When executing in real-mode, the following exceptions are supported:<br/><table border="0" width="50%" cellspacing="1" cellpadding="4" bgcolor="#A3D9F5"><br/><tbody><br/><tr><br/><th bgcolor="#8FB6DF"><span style="font-family: Verdana; font-size: small;"><i>Exception</i></span></th><br/><th bgcolor="#8FB6DF"><span style="font-family: Verdana; font-size: small;"><i>Vector</i></span></th><br/><th bgcolor="#8FB6DF"><span style="font-family: Verdana; font-size: small;"><i>Condition</i></span></th><br/></tr><br/><tr><br/><td><center>Division by Zero</center></td><br/><td><center>0</center></td><br/><td><span style="font-family: Verdana; font-size: small;">Attempting to execute a DIV or an IDIV instruction with a divisor which equals zero.</span></td><br/></tr><br/><tr><br/><td><center>Debug / Single Step</center></td><br/><td><center>1</center></td><br/><td><span style="font-family: Verdana; font-size: small;">Used in conjunction with the debug registers to indicate a breakpoint hit. The processor also issues this interrupt after executing every instruction when the TRAP flag is set.</span></td><br/></tr><br/><tr><br/><td><center>Breakpoint</center></td><br/><td><center>3</center></td><br/><td><span style="font-family: Verdana; font-size: small;">The INT 3 instruction generates this exception. Since the opcode of this instruction is only one byte long, it is often used by debuggers to set a breakpoint in application code. The debugger needs only to replace the first byte of the instruction with the INT 3 opcode (11001100b) and wait for the breakpoint exception to occur. After the exception handler resumes execution and before returning to the debugged application, the debugger sets the INT 3 opcode to the previously overwritten byte and issues an IRET (interrupt return) instruction.</span></td><br/></tr><br/><tr><br/><td><center>Overflow</center></td><br/><td><center>4</center></td><br/><td><span style="font-family: Verdana; font-size: small;">When performing arithmetic instructions with signed operands, the processor set the OF flag to indicate an overflow. The INTO instruction tests this flag and if it is set - generates an exception.</span></td><br/></tr><br/><tr><br/><td><center>Bounds Check</center></td><br/><td><center>5</center></td><br/><td><span style="font-family: Verdana; font-size: small;">The BOUND instruction is used to verify that an array index does not exceed a certain limit. If the limit is exceeded, an exception is generated.</span></td><br/></tr><br/><tr><br/><td><center>Invalid Opcode</center></td><br/><td><center>6</center></td><br/><td><span style="font-family: Verdana; font-size: small;">Occurs when the processor executes one of the reserved opcodes or uses the LOCK prefix improperly. Can also indicate an invalid operand following an opcode.</span></td><br/></tr><br/><tr><br/><td><center>Device Not Available</center></td><br/><td><center>7</center></td><br/><td><span style="font-family: Verdana; font-size: small;">Attempting to execute a floating-point instruction when there is no coprocessor installed. The EM bit of the CR0 register can be cleared to disable this exception.</span></td><br/></tr><br/><tr><br/><td><center>Double Fault</center></td><br/><td><center>8</center></td><br/><td><span style="font-family: Verdana; font-size: small;">An interrupt occurs which has no corresponding entry in the IVT or a second exception is generated while the processor is executing a previously activated exception handler.</span></td><br/></tr><br/><tr><br/><td><center>Stack Exception</center></td><br/><td><center>12</center></td><br/><td><span style="font-family: Verdana; font-size: small;">Stack operation exceeds offset FFFFh or a selector pointing to a non-present segment is loaded intoS.</span></td><br/></tr><br/><tr><br/><td><center>CS, DS, ES, FS, GS Segment Overrun</center></td><br/><td><center>13</center></td><br/><td><span style="font-family: Verdana; font-size: small;">Word memory access at offset FFFFh or an attempt to execute past the end of the code segment.</span></td><br/></tr><br/><tr><br/><td><center>Floating-Point Error</center></td><br/><td><center>16</center></td><br/><td><span style="font-family: Verdana; font-size: small;">An error with the numeric coprocessor (Divide-by-Zero, Underflow, Overflow...).</span></td><br/></tr><br/></tbody><br/></table><br/><span style="font-family: Verdana; font-size: small;"><span style="font-size: xx-small;">Table 2 - Real-Mode exceptions</span></span><br/><br/>Other exceptions exist only in <b>Virtual 8086 Mode</b>:<br/><table border="0" width="50%" cellspacing="1" cellpadding="4" bgcolor="#A3D9F5"><br/><tbody><br/><tr><br/><th bgcolor="#8FB6DF"><span style="font-family: Verdana; font-size: small;"><i>Exception</i></span></th><br/><th bgcolor="#8FB6DF"><span style="font-family: Verdana; font-size: small;"><i>Vector</i></span></th><br/><th bgcolor="#8FB6DF"><span style="font-family: Verdana; font-size: small;"><i>Condition</i></span></th><br/></tr><br/><tr><br/><td><center>Invalid Task State Segment</center></td><br/><td><center>10</center></td><br/><td><span style="font-family: Verdana; font-size: small;">Indicates that one of the checks made during a task switch failed.</span></td><br/></tr><br/><tr><br/><td><center>Segment Not Present</center></td><br/><td><center>11</center></td><br/><td><span style="font-family: Verdana; font-size: small;">Loading one of the segment registers with a selector to a segment marked as not-present.</span></td><br/></tr><br/><tr><br/><td><center>Page Fault</center></td><br/><td><center>14</center></td><br/><td><span style="font-family: Verdana; font-size: small;">Accessing a supervisor page from user privileged code or attempting to access a page which is marked as not-present.</span></td><br/></tr><br/><tr><br/><td><center>Alignment Check</center></td><br/><td><center>17</center></td><br/><td><span style="font-family: Verdana; font-size: small;">Memory access to an unaligned memory location (can only occur while executing ring 3 code).</span></td><br/></tr><br/></tbody><br/></table><br/><span style="font-family: Verdana; font-size: small;"><span style="font-size: xx-small;">Table 3 - Virtual-Mode exceptions</span></span><br/><br/><hr /><br/><br/> <br/><br/><span style="font-family: Verdana; font-size: small;"><span style="font-size: large;"><b>Protected-Mode</b></span></span><br/><br/>Handling interrupts in protected-mode requires setting up a table in memory known as the <b>IDT </b>(Interrupt Descriptor Table). The IDT is somewhat different from the interrupt vector table that exists in real-mode. Instead of being "stuck" at physical address 0, the protected-mode IDT can float around in the linear address space with absolute freedom (although it is possible to change the address of the IVT while in real-mode, it is incompatible with the implementation of the 8086 processor). The linear address of the IDT is determined by a value set into the IDTR register using the LIDT instruction. Each entry in the IDT is 8 bytes long (as opposed to the 4 bytes entries of the IVT) and can contain one of three gate descriptors:<br/><ul><br/> <li>A task gate - Causes a task switch to occur.</li><br/> <li>An interrupt gate - Control is transferred to the interrupt handler with interrupts disabled.</li><br/> <li>A trap gate - Control is transferred to the interrupt handler (the interrupt flag remains unchanged).</li><br/></ul><br/>The following figure presents the internal structure of a trap gate entry:<br/><br/><img alt="" src="http://www.internals.com/articles/protmode/trapgate.gif" /><br/><span style="font-size: xx-small;">Figure 1 - Structure of a trap gate entry</span><br/><br/>Trap and interrupt gates have much in common since they are both used for control transfers between different privilege levels. The selector and offset fields specified in these gate descriptors are used to locate and execute the interrupt handler code. A control transfer is only permitted to a code residing in the same or a higher privilege level but never to a lower privileged one.<br/><br/><span style="font-family: Verdana; font-size: small;"><span style="font-size: medium;"><b>Software Interrupts</b></span></span><br/><br/>Software interrupts are still widely used by protected-mode operating systems in order to publish their internal services to the external world. However, most of these interfaces are now wrapped by functions and cannot be accessed directly (although it's possible, it's not recommended). For instance, Windows NT uses the undocumented interrupt 2Eh to allow control transfers between its user mode and kernel mode components. Whenever a non-privileged Windows application issues a call to an API function, the system routes the call until it reaches an INT 2Eh instruction. The IDT gate corresponding to this interrupt points to a handler inside ntoskrnl, which performs the required privileged operations on behalf of the application. Windows 95 and 98 use a similar technique to hop between user and kernel mode, but rely upon INT 30h instead of using INT 2Eh.<br/><br/><span style="font-family: Verdana; font-size: small;"><span style="font-size: medium;"><b>Hardware Interrupts</b></span></span><br/><br/>Hardware interrupts in protected-mode behave in the same manner as described in the real-mode section. The only major difference is that when executing in protected-mode, the processor consults its IDT rather than searching the real-mode IVT for the address of the interrupt handler.<br/><br/><span style="font-family: Verdana; font-size: small;"><span style="font-size: medium;"><b>Exceptions</b></span></span><br/><br/>Most of the information which was presented in the previous sections, applies to protected-mode as well. However, exception 13 (General Protection Fault) has a wider meaning in protected-mode and can indicate additional conditions than those defined for real-mode.<br/><br/>That's it. More information about the implementation of interrupts and exceptions in protected-mode can be obtained from the "Pentium Processor.<br/><br/> 

Computer Organisation Interrupts and Exceptions

Introduction Much of the functionality embedded inside a personal computer is implemented by hardware devices other than the processor. For ...

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Input Output organisation

<h1><span class="Apple-style-span"><strong>Accessing I/O Devices:-</strong></span></h1><br/><ul><br/> <li>Most modern computers use single bus arrangement for connecting I/O devices to CPU & Memory.</li><br/> <li>The bus enables all the devices connected to it to exchange information.</li><br/> <li>Bus consists of 3 set of lines : Address, Data & Control Lines.</li><br/> <li>Processor places a particular address (unique for an I/O Device) on address lines.</li><br/> <li>Device which recognizes this address responds to the commands issued on the Control lines.</li><br/> <li>Processor requests for either Read/Write.</li><br/> <li>The data will be placed on Data lines</li><br/></ul><br/><h1><span class="Apple-style-span"><strong>I/O INTERFACE:-</strong></span><strong><a href="http://k-developers.com/wp-content/uploads/2015/12/iointerface.png"><img alt="iointerface" class="size-full wp-image-100 aligncenter" height="377" src="http://k-developers.com/wp-content/uploads/2015/12/iointerface.png" width="851" /></a></strong></h1><br/><div>1) It is a special hardware used to connect the I/O device to the bus , i.e, I/O interface.</div><br/><div>2)The I/O module has following sections:-</div><br/><ul><br/> <li><strong>Address decoder:-</strong> It enables the device to recognize its address when this address appears on the address lines.</li><br/> <li><strong>Data register:-</strong> The data register holds the data being transferred to or from the processor.</li><br/></ul><br/><div>3) The status register contains information relevant to the operation of the I/O module.</div><br/><div>* Both the data and status register are connected to the data bus.</div><br/><div><a href="http://k-developers.com/wp-content/uploads/2015/12/iomodule.png"><img alt="iomodule" class="size-full wp-image-101 aligncenter" height="331" src="http://k-developers.com/wp-content/uploads/2015/12/iomodule.png" width="692" /></a></div><br/><div></div><br/><h2><strong>MODES OF DATA TRANSFER:-</strong></h2><br/><div><strong>1.Programmed I/O Mode:-</strong></div><br/><div>1) In programmed I/O mode data are exchanged between the processor and the I/O module.  When a processor is executing a program and encounters an instruction relating to I/O, it executes that instruction by issuing a command to that appropriate I/O module. With programmed I/O the I/O module will perform the requested action and then set the appropriate bit in the I/O status register.</div><br/><div>2) The I/O module takes no further action to alert the processor (it doesn't interrupt the processor).</div><br/><div>3) The I/O commands issued by the processor to the I/O module</div><br/><ul><br/> <li>Test</li><br/> <li>Control</li><br/> <li>Read</li><br/> <li>Write</li><br/></ul><br/><div><strong>2.Memory Mapped I/O:-</strong></div><br/><div>1) There is a single address space for memory location and I/O devices.( the address space is shared)</div><br/><div>2) With memory mapped I/O a single read line a single write line are needed on the bus. The bus may be equipped with memory read and write plus Input and output command lines.</div><br/><div>3) Now the command lines specifies whether the address refers to memory location or an I/O device.</div><br/><div>4) Most CPU uses memory mapped I/O.</div><br/><div>5) Always CPU assigns address to memory some of memory space is stolen and assigned to I/O device.</div><br/><div>6) It deals with fewer address lines.</div><br/><div><a href="http://k-developers.com/wp-content/uploads/2015/12/MEMORYMAPED.png"><img alt="MEMORYMAPED" class="size-full wp-image-102 aligncenter" height="318" src="http://k-developers.com/wp-content/uploads/2015/12/MEMORYMAPED.png" width="709" /></a></div><br/><div></div><br/><div><strong>3.Interrupt Driven I/O:-</strong></div><br/><div>1) In this method the program issues an I/O command and than continues to execute until it is interrupted by the I/O hardware to signal the end of I/O operation.</div><br/><div>2) Here the program enters a wait loop in which it repeatedly checks the device status. During this process the processor is not performing any useful computation.</div><br/><div>3) There are many situations where tasks can be performed while waiting for an I/O device to be ready, to allow this the I/O device should alert the processor when it becomes ready. It can be done by sending a hardware signal called an <strong>interrupt.</strong></div><br/><div>4) The routine executed in response to an interrupt request is called<strong> Interrupt Service Routine </strong>(ISR).</div><br/><div>5) The processor first completes execution of instruction then it loads the program counter(pc) with the address of first instruction of ISR.</div><br/><h3><strong>4.Direct Memory Access:-</strong></h3><br/><div>1) In this method the input and output devices read/write information from the main memory without interference of the CPU through the system bus.</div><br/><div>2) For I/O transfer, processor determines the status of I/O by:</div><br/><ul><br/> <li>Polling</li><br/> <li>Waiting for interrupt signal.</li><br/></ul><br/><div>3) Considerable Overhead is incurred in above I/O transfer processing.</div><br/><div>4) By DMA approach , large blocks of data at high speed can be sent between external device and main memory.</div><br/><div><strong>DMA CONTROLLER:-</strong></div><br/><div>1) It allows the data transfer between I/O device and memory.</div><br/><div>2) DMA controllers acts a processor but it is controlled by the CPU. To initiate the transfer of a block of words, the processor sends the following data to controller</div><br/><ul><br/> <li>Starting address of memory block</li><br/> <li>The word count</li><br/> <li>Control to specify the mode of transfer such as read or write.</li><br/> <li>A control to start the DMA transfer.</li><br/></ul><br/><div>3) The DMA controller performs the required I/O operation and send a interrupt to the processor upon completion.</div><br/><div></div><br/><div> <a href="http://k-developers.com/wp-content/uploads/2015/12/DMA.png"><img alt="DMA" class="size-full wp-image-103 aligncenter" height="377" src="http://k-developers.com/wp-content/uploads/2015/12/DMA.png" width="662" /></a></div><br/><h2><strong><span class="Apple-style-span">Use Of DMA controller in Computer System</span></strong></h2><br/><div><span class="Apple-style-span">1) DMA device have higher priority then processor over BUS control.</span></div><br/><div>2) Types of DMA Transfer:-</div><br/><ul><br/> <li>Cycle stealing</li><br/> <li>Burst mode</li><br/></ul><br/><div><strong>Cycle Stealing:-</strong></div><br/><div>DMA controller ‘steals’ memory cycles from the processor though processor originates most memory access.</div><br/><div><b>Burst</b><strong> mode:- </strong></div><br/><div>The DMA controller may be given exclusive access to the main memory to transfer a block of data without interruption.</div><br/><div><strong>Conflicts Of DMA</strong>:-</div><br/><ul><br/> <li>Conflict between processor and DMA</li><br/> <li>Two DMA Controller try to access the BUS at same time to access the main memory.</li><br/></ul><br/><br/><hr /><br/><br/> 

Computer Organisation I/O Organisation Input Output organisation

Accessing I/O Devices:- Most modern computers use single bus arrangement for connecting I/O devices to CPU & Memory. The bus enables...

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